83140-580-01 c ISP1040B 1 features n compliance with ansi scsi standard x3.131-1994 n compliance with ansi scsi con?gured automatically (scam) protocol levels 1 and 2 n compliance with ansi x3t10/855d scsi-3 parallel interface (spi) standard n compliance with ansi x3t10/1071d fast-20 standard n onboard risc processor to execute operations at the i/o control block level from the host memory n supports fast, wide, and ultra (fast-20) scsi data transfer rates n scsi initiator and target modes of operation n 32-bit, intelligent bus master, dma pci bus interface n scsi operations executed from start to ?nish without host intervention n simultaneous, multiple logical threads n jtag boundary scan support product description the ISP1040B is a single-chip, highly integrated, bus master, scsi i/o processor for use in scsi initiator-type applications. the device interfaces the pci bus to a wide, ultra scsi bus and contains an onboard risc processor. the ISP1040B is a fully autonomous device, capable of managing multiple i/o operations and associated data transfers from initiation to completion without host cpu intervention. the ISP1040B block diagram is illustrated in ?gure 1. risc i/o data bus figure 1. ISP1040B block diagram data channel sxp scsi engine pci interface host memory host software driver request queue response queue 32-bit pci bus iocbs fifo wcs sequencers control data fifo command fifo dma control mailbox registers risc register file alu boot code memory interface 8/16-bit data 16 address 16 external code/data memory ISP1040B command buffer message buffer sxp code registers parallel scsi bus ctrl/config registers qlogic corporation ISP1040B intelligent scsi processor data sheet www..net
2 ISP1040B 83140-580-01 c qlogic corporation isp initiator and target firmware the ISP1040B ?rmware implements a cooperative, multitasking host adapter that provides the host system with complete scsi command and data transport capabilities, thus freeing the host system from the demands of the scsi bus protocol. the ISP1040B ?rmware provides two interfaces to the host system: the command interface and the scsi transport interface. the single-threaded command interface facilitates debugging, con?guration, and error recovery. the multithreaded scsi transport interface maximizes use of the scsi and host buses. the ISP1040B can switch between initiator and target modes. i/o subsystem organization to maximize i/o throughput and improve host and scsi bus utilization, the ISP1040B incorporates a high-speed, proprietary risc processor; an intelligent scsi bus controller (scsi executive processor [sxp]); and a host bus, dual-channel dma controller. the scsi bus controller and the host bus dma controller operate independently and concurrently under control of the onboard risc processor for maximum system performance. the ISP1040B risc interface requires external program data memory. the complete i/o subsystem solution using the ISP1040B and associated supporting memory devices is shown in ?gure 2. interfaces the ISP1040B supports the following interfaces: n pci bus n risc processor n scsi executive processor pins that support these interfaces and other chip operations are shown in ?gure 3. pci bus interface the ISP1040B pci bus interface supports the following: n 128-byte data dma fifo and 64-byte command dma fifo with threshold control n 16-bit target mode n dma fifo management, data alignment, data assembly, and data disassembly n pci local bus speci?cation revision 2.1 compliant n support for subsystem id and subsystem vendor id n dual voltage (3.3v and 5.0v) pci i/o buffers n flash rom support the ISP1040B is designed to interface directly to the pci local bus and operate as a 32-bit dma master. this function is accomplished through the pci bus interface unit (pbiu) containing an onboard dma controller. the pbiu generates and samples pci bus control signals, generates host memory addresses, and facilitates data transfers between host memory and the onboard dma fifo. the pbiu also allows the host to access the ISP1040B internal registers and communicate with the onboard risc processor through the pci bus target mode operation. the ISP1040B onboard dma controller consists of two independent dma channels that initiate transactions on the pci bus and transfer data between the memory and dma fifo. the two dma channels are the command dma channel and the data dma channel. the command dma channel is used mainly by the risc processor for small transfers such as fetching commands from and writing status information to the host memory over the pci bus. the data dma channel transfers data between the scsi bus and the pci bus. the pbiu internally arbitrates between the data dma channel and the command dma channel and alternately services them. each dma channel has a set of dma registers that are programmed for transfers by the risc processor. ISP1040B scsi 16 scsi targets target target pci i/f scsi i/f risc code/data memory pci bus pci host memory iocb data 32 figure 2. i/o subsystem design using the ISP1040B
83140-580-01 c ISP1040B 3 qlogic corporation risc processor interface the ISP1040B risc processor interface supports the following: n programmable cycle time for external memory access n internal 16-bit wide data paths n execution of multiple i/o control blocks from the host memory n management of onboard host bus dma controller and scsi bus controller n reduced host intervention and interrupt overhead n capacity to generate one interrupt per i/o operation the onboard risc processor enables the ISP1040B to handle complete i/o transactions with no intervention from the host. the ISP1040B risc processor controls the chip figure 3. ISP1040B functional signal grouping extboot risc interface vdd vss power and ground misc control bsy cd diffm scsi interface ISP1040B riscstb/jtag esc1-0 raddr15-0 if/vdet ack atn io msg req rst sd15-0 sdp1-0 sel trig/60mhz tstout/tdo frame stop trdy devsel perr idsel serr irdy reset clk riscoe we rdata15-0 testmode0/tdi reset cbe3-0 par inta nvdati nvcs nvdato/subid nvclk/3v nvram control bios prom pdata7-0 pod bsyled gpio3-0 rdpar diffs earb esd eig etg ebsy esel erst scsi differential interface pci interface ad31-0 bclk bgnt breq flash rom fr oe fr we testmode1/tms testmode2/tck
4 ISP1040B 83140-580-01 c qlogic corporation interfaces; executes simultaneous, multiple input/output control blocks (iocbs); and maintains the required thread information for each transfer. scsi executive processor interface the ISP1040B sxp interface supports the following: n scam level 1 and level 2 support r 32-byte fifo with parity pass-through option r command, status, message in, and message out buffers r device information storage area n scsi synchronous transfer rates of 40 mbytes/sec (requires 60-mhz clock) n scsi asynchronous transfer rate of 12 mbytes/sec n programmable scsi processor r specialized instruction set with 16-bit microword r 384-bit by 16-bit internal control store ram n diagnostic support the sxp provides an autonomous, intelligent scsi interface capable of handling complete scsi operations. the sxp interrupts the risc processor only to handle higher level functions such as threaded operations or error handling. packaging the ISP1040B is available in a 208-pin plastic quad ?at pack (pqfp). package dimensions are shown in ?gure 4. figure 4. ISP1040B mechanical drawings index mark pin 1 pin 53 pin 104 pin 208 pin 52 pin 105 pin 156 pin 157 28.0 0.1 30.6 0.25 30.6 0.25 note: all dimensions are in millimeters. see detail a detail a 0.33 + 0.1 0.20 + 0.1 0.15 4.07 maximum 0.50 bsc 0.56 + 0.1 4 typical +0.10 -0.05 28 0.1 ?february 5, 1997 qlogic corporation, 3545 harbor blvd., costa mesa, ca 92626, (800) on-chip-1 or (714) 438-2200 speci?cations are subject to change without notice. qlogic is a trademark of qlogic corporation.
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